This invention relates generally to semiconductor circuits and more particularly, it relates to a unitary multiplexer-decoder circuit which is formed as an integrated circuit on a single semiconductor chip to provide a higher speed of operation.
In general, a block diagram of the prior art is illustrated in FIG. 1 which includes a plurality of multiplexer circuits 2 and a plurality of decoder circuits 4. Each of the multiplexer circuits is formed from a schematic diagram of FIG. 2(a), and each of the decoder circuits is formed from a schematic diagram of FIG. 2(b). As can be seen, plurality of data input signals either A.sub.0, A.sub.1 . . . through A.sub.n or B.sub.0, B.sub.1 . . . through B.sub.n are required to be passed through the plurality of multiplexer circuits 2 whose outputs are then decoded by the respective plurality of decoders 4. A common control signal S is applied to the control input of each multiplexer circuit so as to selectively pass either the data inputs A.sub.0 . . . A.sub.n or the data inputs B.sub.0 . . . B.sub.n to generate output signals Y.sub.0 . . . Y.sub.2n+1 of the decoder circuits. For example, when S=0 the data inputs A.sub.0 . . . A.sub.n are selected and when S=1 the data inputs B.sub.0 . . . B.sub.n are selected.
Thus, the data input signals are required to pass through two emitter coupled logic (ECL) gates (one in the multiplexer and one in the decoder) which increase the propagation delays. Further, the number of current sources required for the multiplexer circuits is 3n and the number of current sources required for the decoder circuits is 2.sup.n+1. This gives a total number of 3n+2.sup.n+1 current sources where n is the number of data input signals.
It would therefore be desirable to provide a unitary multiplexer-decoder circuit which is formed as an integrated circuit on a single semiconductor chip which has only a signle gate delay and has a significantly reduced number of current sources and components, thereby increasing the efficienty and speed of operation.